PIC18F4515T-I/PT【PDF 60/234 页】IC MCU FLASH 24KX16 44TQFP

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PIC18F2X1X/4X1X

DS39636D-page 154

2009 Microchip Technology Inc.

16.3.1

REGISTERS

The MSSP module has four registers for SPI mode

operation. These are:

MSSP Control Register 1 (SSPCON1)

MSSP Status Register (SSPSTAT)

Serial Receive/Transmit Buffer Register

(SSPBUF)

MSSP Shift Register (SSPSR) – Not directly

accessible

SSPCON1 and SSPSTAT are the control and status

registers in SPI mode operation. The SSPCON1

the SSPSTAT are read-only. The upper two bits of the

SSPSTAT are read/write.

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

During transmission, the SSPBUF is not double-

buffered. A write to SSPBUF will write to both SSPBUF

and SSPSR.

REGISTER 16-1:

SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0

R-0

SMP

CKE

D/A

R/W

bit 7

bit 0

bit 7

SMP: Sample bit

SPI Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI operation is used in Slave mode.

bit 6

CKE: SPI Clock Select bit

1 = Transmit occurs on transition from active to Idle clock state

0 = Transmit occurs on transition from Idle to active clock state

Note:

Polarity of clock state is set by the CKP bit (SSPCON1<4>).

bit 5

D/A: Data/Address bit

Used in I2C mode only.

bit 4

P: Stop bit

Used in I2C mode only. This bit is cleared when the MSSP module is disabled; SSPEN is

cleared.

bit 3

S: Start bit

Used in I2C mode only.

bit 2

R/W: Read/Write bit Information

Used in I2C mode only.

bit 1

UA: Update Address bit

Used in I2C mode only.

bit 0

BF: Buffer Full Status bit (Receive mode only)

1 = Receive complete, SSPBUF is full

0 = Receive not complete, SSPBUF is empty

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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